IBIS Macromodel Task Group Meeting date: 16 August 2022 Members (asterisk for those attending): Achronix Semiconductor: Hansel Dsilva Amazon: John Yan ANSYS: Curtis Clark * Wei-hsing Huang Cadence Design Systems: Ambrish Varma * Jared James Google: Zhiping Yang Intel: * Michael Mirmak Kinger Cai Chi-te Chen Alaeddin Aydiner Keysight Technologies: * Fangyi Rao Majid Ahadi Dolatsara * Ming Yan Radek Biernacki Rui Yang Luminous Computing David Banas Marvell Steve Parker Mathworks (SiSoft): * Walter Katz Mike LaBonte Micron Technology: * Randy Wolff * Justin Butterfield Missouri S&T Chulsoon Hwang SAE ITC Michael McNair Siemens EDA (Mentor): * Arpad Muranyi Teraspeed Labs: * Bob Ross Zuken USA: * Lance Wang The meeting was led by Arpad Muranyi. Randy Wolff took the minutes. -------------------------------------------------------------------------------- Opens: - None. ------------- Review of ARs: - Michael Mirmak to send his Dual Input Rx Questions presentation to the ATM list - done -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the August 9th meeting. Michael moved to approve the minutes. Randy seconded the motion. There were no objections. -------------- New Discussion: Proposal for a new keyword [Clock Group]: Michael shared the BIRD draft shown in the last meeting. This avoids using [Component] or separate files to organize the clock and data relationships that are possible in a memory controller. This does not eliminate [Clock Pins] but creates two different hierarchies. Arpad wondered if there was a better way to do it. Michael did not want to change how [Clock Pins] is used today. He thought [Clock Group] would be coded to be a hidden keyword that would be created by EDA tools even if it wasn't there and only one [Clock Pins] was in the IBIS file. Arpad asked if there were any models in existence with [Clock Pins]. Michael said there were not. Michael noted there is a parser bug that needs to be fixed causing issues with [Clock Pins] and [Model Selector]. Arpad asked if there could be a requirement for [Clock Group]. Michael said you could have a 7.1 model without [Clock Pins] but a later version of IBIS could require [Clock Group]. Bob thought the parser could be made to handle this case. Walter asked about a configuration case. A motherboard has 4 controllers with 96-bit buses going to 2-rank 2-DIMM systems. He asked if x4 and x8 memories can be mixed on a DQ bus. Michael noted this is the exact scenario for the need of [Clock Group]. If all 4 controllers are identical and use the same IBIS file, then at simulation time the model should contain several [Clock Group]s with different names for x4 and x8. The user would select the [Clock Group] for each controller instance. There can be mixes of x4 and x8 DRAM. Randy noted you don't have x4 and x8 mixed on a DIMM, but you can have x4 and x8 based DIMMs mixed in a system. Michael noted controllers may limit all the permutations they support. Fangyi asked if the Clock Groups are exclusive. Michael noted you can't have more than one group active, since they are for a specific architecture that is grouping pins differently. Walter noted this kind of a group is a configuration of the memory that defines the requirement for the [Clock Group]s. This is a hardware configuration. A [Model Selector] for ODT has different ODT selected depending on the transfer. This is more dynamic behavior. Bob suggested naming the keyword [Clock Configuration] since it is a configuration and different from other usage of "Group" in IBIS. Randy showed a picture on page 3 of a Micron technical note of a DDR3 system mixing x4 and x8 devices and described the use of TDQS for proper terminations of unused strobes on x8 based DIMMs. https://urldefense.proofpoint.com/v2/url?u=https-3A__media-2Dwww.micron.com_-2D_media_client_global_documents_products_technica&d=DwIGAg&c=nKjWec2b6R0mOyPaz7xtfQ&r=DcQR-qLpQg5lIreuM6-NYECRIAFXt268PRNS5WO043M&m=H5bNj9oVuM4Xb5q2JIKkDrfVk2rN9FZjprdMIlre7H2iuwRIw0pNaODpUMDgnyoY&s=EGzi1BguXROtuOE2H9w3_Mo3OYualaJyXVS0W9Cytew&e= l-note/dram/tn4106_tdqs.pdf?rev=04f7fcf57b454bb19b51840c46c7d666 Walter did not think the [Clock Group]s for the controller could really describe this situation. Michael planned to send more information to the reflector for feedback. #IFDEF configurations: Arpad noted the goal was to eliminate the need for complicated logic and GUI controls to make selections. If there became too many #ifdef statements in a model that could become cumbersome. Walter noted the model maker will put the #ifdef statements into the IBIS file. The user then selects settings for each of the parameters. Arpad asked if the purpose is to make the GUI development easier, then will it make the user have to make lots of settings in a separate parameter file. Walter said there would be few parameters such as speed grade to set. Walter added we can't use #ifdef statements for [Clock Group]s because those are more complicated. - Michael: Motion to adjourn. - Walter: Second. - Arpad: Thank you all for joining. AR: None ------------- Next meeting: 23 August 2022 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives